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SH7021 Datasheet(PDF) 299 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 299 Page - Renesas Technology Corp |
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299 / 509 page ![]() RENESAS 283 H' FFFF H' 0000 CK TCNT Overflow signal OVF OVI Figure 10.56 Timing of Setting OVF 10.5.2 Clear Timing of Status Flags The status flags are cleared by a write cycle in which 1 is read on the CPU and then 0 is written to it. This timing is shown in figure 10.57. T1 T3 T2 CK Address IMF, OVF TSR address TSR write cycle Figure 10.57 Timing of Status Flag Clearing |
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