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SH7021 Datasheet(PDF) 301 Page - Renesas Technology Corp |
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SH7021 Datasheet(HTML) 301 Page - Renesas Technology Corp |
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301 / 509 page ![]() RENESAS 285 10.6 Notes and Precautions This section describes contention and other matters requiring special attention during ITU operations. 10.6.1 Contention between TCNT Write and Clear If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes priority and the write is not performed. The timing is shown in figure 10.58. T1 T3 T2 CK Address Internal write signal Counter clear signal TCNT TCNT write cycle by CPU TCNT address N H' 0000 Figure 10.58 Contention between TCNT Write and Clear |
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