SH7021 datasheet(318/509 Pages) RENESAS

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Table 10.22 ITU Operating Modes (Channel 4) (cont)

Counter Clear Function

TSNC

TMDR

TFCR

TOCR

TIOR4

TCR4

Operating

Mode

Sync

MDF FDIR PWM

Comp

PWM

Reset

Sync

PWM

Buf-

fer

Output

Level

Select IOA

IOB

Clear

Select

Clock

Select

Synch-

ronized

clear

SYNC4

= 1

——

√

CMD1

= 1,

CMD1

= 0

inhibit

√*3

√

—

√√

CCLR1

= 1

CCLR0

= 1

√

Comple-

mentary

PWM

√*2

———

CMD1

= 1

CMD0

= 0

CMD1

= 1

CMD0

= 0

√√

——

CCLR1

= 0

CCLR0

= 0

√*4

Reset

synchron-

ized PWM

√

———

CMD1

= 1

CMD0

= 1

CMD1

= 1

CMD0

= 1

√√

——

√*5

Buffer

(BRA)

√

——

√√

√

BFA4

= 1,

others

free

—

√√

√

Buffer

(BRB)

√

——

√√

√

BFB4

= 1,

others

free

—

√√

√

√: Settable, —: Setting does not affect current mode

Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and

compare match B occur simultaneously, the compare match signal is inhibited.

2. When set for complementary PWM mode, do not simultaneously set channel 3 and

channel 4 to function synchronously.

3. Counter clearing works with the reset-synchronized PWM mode, but TCNT4 runs

independently. The output waveform is not affected.

4. Clock selection when the complementary PWM mode is set should be the same for

channels 3 and 4.

5. In the reset-synchronized PWM mode, TCNT4 runs independently. The output

waveform is not affected.

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