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R8C/15 Datasheet(PDF) 41 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 41 Page - Renesas Technology Corp |
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41 / 277 page ![]() R8C/14 Group, R8C/15 Group 6. Voltage Detection Circuit Rev.2.10 Jan 19, 2006 Page 29 of 253 REJ09B0164-0210 Figure 6.5 VW1C Register Voltage Monitor 1 Circuit Control Register (1) Symbol Address After Reset(2) VW1C 0036h Hardw are Reset : 0000X000b Pow er-On Reset, Voltage Monitor 1 Reset : 0100X001b Bit Symbol Bit Name Function RW NOTES : 1. 2. 3. b3 b2 Set to “0”. RW b1 b0 0 b7 b6 b5 b4 VW1C0 RW Voltage Monitor 1 Reset Enable Bit(3) 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) RW VW1C2 Reserved Bit VW1C1 Voltage Monitor 1 Digital Filter Disable Mode Select Bit — (b3) Reserved Bit VW1F1 RW Sampling Clock Select Bit b5 b4 0 0 : fRING-S divide-by-1 0 1 : fRING-S divide-by-2 1 0 : fRING-S divide-by-4 1 1 : fRING-S divide-by-8 VW1F0 RW When read, its content is indeterminate. RO VW1C6 Voltage Monitor 1 Circuit Mode Select Bit When the VW1C0 bit is set to “1” (enables voltage monitor 1 reset), set to “1”. RW VW1C7 Voltage Monitor 1 Reset Generation Condition Select Bit When the VW1C1 bit is set to “1” (digital filter disabled mode), set to “1”. RW Set the PRC3 bit in the PRCR register to “1” (w rite enable) before w riting to this register. When rew riting the VW1C register, the VW1C2 bit may be set to “1”. Set the VW1C2 bit to “0” after rew riting the VW1C register. The value after reset remains unchanged in softw are reset, w atchdogi timer reset and voltage monitor 2 reset. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to “1” (voltage detection 1 circuit enabled). Set the VW1C0 bit to “0” (disable), w hen the VCA26 bit is set to “0” (voltage detection 1 circuit disabled). |
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