R8CSLASH15 datasheet(53/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

9. Clock Generation Circuit

Rev.2.10

Jan 19, 2006

Page 41 of 253

REJ09B0164-0210

Figure 9.3

CM1 Register

System Clock Control Register 1

(1)

Symbol

Address

After Reset

CM1

0007h

20h

Bit Symbol

Bit Name

Function

NOTES :

When entering stop mode from high or middle speed mode, this bit is set to “1” (drive capacity HIGH).

Set the PRC0 bit in the PRCR register to “1” (w rite enable) before rew riting to this register.

b7 b6 b5 b4 b3 b2 b1 b0

CM10

All Clock Stop Control Bit(4,7,8)

0 : Oscillates clock

1 : Stops all Clocks (stop mode)

—

(b1)

Reserved Bit

Set to “0”

—

(b2)

Reserved Bit

Set to “0”

CM13

Port XIN-XOUT Sw itch Bit(7)

0 : Input port P4_6, P4_7

1 : XIN-XOUT Pin

CM14

Low -Speed On-Chip Oscillation Stop

Bit(5,6,8)

0 : Low -speed on-chip oscillator on

1 : Low -speed on-chip oscillator off

CM15

XIN-XOUT Drive Capacity Select Bit(2) 0 : LOW

1 : HIGH

CM17

b7 b6

0 0 : No division mode

0 1 : Divide-by-2 mode

1 0 : Divide-by-4 mode

1 1 : Divide-by-16 mode

System Clock Division Select Bit 1(3)

CM16

When the CM10 bit is set to “1” (stop mode) or the CM05 bit in the CM0 register to “1” (main clock stops) and the

CM13 bit is set to “1” (XIN-XOUT pin), the XOUT (P4_7) pin becomes “H”.

When the CM13 bit is set to “0” (input ports, P4_6, P4_7), the P4_7 (XOUT) enters input mode.

In count source protect mode (Refer to 12.2 Count Source Protect Mode), the value remains unchanged even if

the CM10 and CM14 bits are set.

When the CM06 bit is set to “0” (CM16, CM17 bits enabled), this bit becomes enabled.

If the CM10 bit is “1” (stop mode), the internal feedback resistor becomes disabled.

When the OCD2 bit is set to “0” (selects main clock), the CM14 bit is set to “1” (stops low -speed

on-chip oscillator). When the OCD2 bit is set to “1” (selects on-chip oscillator clock), the CM14 bit is set to “0”

(low -speed on-chip oscillator on). It remains unchanged even if it is set to “1”.

When using the voltage detection interrupt, CM14 bit is set to “0” (low -speed on-chip oscillator on).

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