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R8C/15 Datasheet(PDF) 60 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 60 Page - Renesas Technology Corp |
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60 / 277 page ![]() R8C/14 Group, R8C/15 Group 9. Clock Generation Circuit Rev.2.10 Jan 19, 2006 Page 48 of 253 REJ09B0164-0210 9.4 Power Control There are three power control modes. All modes other than wait and stop modes are referred to as normal operating mode. 9.4.1 Normal Operating Mode Normal operating mode is further separated into four modes. In normal operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source after switching needs to be stabilized and oscillated. If the new clock source is the main clock, allow sufficient wait time in a program until an oscillation is stabilized before exiting. NOTES: 1. The low-speed on-chip oscillator is used as the on-chip oscillator clock when the CM14 bit in the CM1 register is set to “0” (low-speed on-chip oscillator on) and the HRA01 bit in the HRA0 register is set to “0”. The high-speed on-chip oscillator is used as the on-chip oscillator clock when the HRA00 bit in the HRA0 register is set to “1” (high-speed on-chip oscillator A on) and the HRA01 bit in the HRA0 register is set to “1”. Table 9.2 Setting and Mode of Clock Associated Bit Modes OCD Register CM1 Register CM0 Register OCD2 CM17, CM16 CM13 CM06 CM05 High-Speed Mode 0 00b 1 0 0 Medium- Speed Mode divide-by-2 0 01b 1 0 0 divide-by-4 0 10b 1 0 0 divide-by-8 0 − 11 0 divide-by-16 0 11b 1 0 0 High-Speed, Low-Speed On-Chip Oscillator Mode(1) no division 1 00b − 0 − divide-by-2 1 01b − 0 − divide-by-4 1 10b − 0 − divide-by-8 1 −− 1 − divide-by-16 1 11b − 0 − |
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