R8CSLASH15 datasheet(79/277 Pages) RENESAS

79 / 277 page

R8C/14 Group, R8C/15 Group

11. Interrupt

Rev.2.10

Jan 19, 2006

Page 67 of 253

REJ09B0164-0210

11.1.6.8

Returning from an Interrupt Routine

When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC,

which have been saved to the stack, are automatically returned. The program, executed before the

interrupt request has been acknowledged, starts running again.

Return the register saved by a program in an interrupt routine using the POPM instruction or others

before the REIT instruction.

11.1.6.9

Interrupt Priority

If two or more interrupt requests are generated while executing one instruction, the interrupt with the

higher priority is acknowledged.

Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral

functions). However, if two or more maskable interrupts have the same priority level, their interrupt

priority is resolved by hardware, with the higher priority interrupt acknowledged in hardware.

The priority levels of special interrupts such as reset (reset has the highest priority) and watchdog

timer are set by hardware. Figure 11.9 shows the Interrupt Priority Levels of Hardware Interrupt.

The interrupt priority does not affect software interrupts. The microcomputer jumps to the interrupt

routine when the instruction is executed.

Figure 11.9

Interrupt Priority Levels of Hardware Interrupt

Reset

Watchdog Timer

Oscillation Stop Detection

Voltage Monitor 2

Peripheral Function

Single Step

Address Match

High

Low

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