R8CSLASH15 datasheet(94/277 Pages) RENESAS

94 / 277 page

R8C/14 Group, R8C/15 Group

12. Watchdog Timer

Rev.2.10

Jan 19, 2006

Page 82 of 253

REJ09B0164-0210

12.2

When Count Source Protection Mode Enabled

The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source

protection mode is enabled. If the CPU clock stops when the program is out of control, the clock can be

supplied to the watchdog timer. Table 12.3 lists the Specification of Watchdog Timer (When Count

Source Protection Mode is Enabled).

NOTES:

1. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write “0” to the bit

0 of the address 0FFFFh by a flash writer.

2. Even if writing “0” to the CSPROINI bit in the OFS register, the CSPRO bit is set to “1”. The

CSPROINI bit cannot be changed by a program. When setting the CSPROINI bit, write “0” to the bit

7 of the address 0FFFFh by a flash writer.

Table 12.3

Specification of Watchdog Timer (When Count Source Protection Mode is Enabled)

Item

Specification

Count Source

Low-speed on-chip oscillator clock

Count Operation

Decrement

Period

Count value of watchdog timer (4096)

Low-speed on-chip oscillator clock

e.g. Period is approximately 32.8ms when the low-speed on-chip

oscillator clock is 125 kHz

Count Start Condition

The WDTON bit(1) in the OFS register (0FFFFh) selects the operation

of the watchdog timer after reset.

• When the WDTON bit is set to “1” (watchdog timer is in stop state

after reset)

The watchdog timer and prescaler stop after reset and the count

starts by writing to the WDTS register

• When the WDTON bit is set to “0” (watchdog timer starts

automatically after reset)

The watchdog timer and prescaler start counting automatically after

reset

Reset Condition of Watchdog

Timer

• Reset

• Write “00h” to the WDTR register before writing “FFh”

• Underflow

Count Stop Condition

None (the count does not stop in wait mode after the count starts. The

microcomputer does not enter stop mode)

Operation at the time of

Underflow

Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)

• When setting the CSPPRO bit in the CSPR register to “1” (count

source protection mode is enabled)(2), the following are set

automatically

- Set 0FFFh to the watchdog timer

- Set the CM14 bit in the CM1 register to “0” (low-speed on-chip

oscillator on)

- Set the PM12 bit in the PM1 register to “1” (The watchdog timer is

reset when watchdog timer underflows)

• The following states are held in count source protection mode

- Writing to the CM10 bit in the CM1 register disables (It remains

unchanged even if it is set to “1”. The microcomputer does not

enter stop mode)

- Writing to the CM14 bit in the CM1 register disables (It remains

unchanged even if it is set to “1”. The low-speed on-chip oscillator

does not stop)

R8C/15 Datasheet(PDF) 94 Page - Renesas Technology Corp

R8C/15 Datasheet(HTML) 94 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL