R8CSLASH15 datasheet(81/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

11. Interrupt

Rev.2.10

Jan 19, 2006

Page 69 of 253

REJ09B0164-0210

11.2

INT Interrupt

11.2.1

INT0 Interrupt

The INT0 interrupt is generated by an INT0 input. When using the INT0 interrupt, the INT0EN bit in

the INTEN register is set to “1” (enable). The edge polarity is selected using the INT0PL bit in the

INTEN register and the POL bit in the INT0IC register.

Inputs can be passed through a digital filter with three different sampling clocks.

The INT0 pin is shared with the external trigger input pin of timer Z.

Figure 11.11 shows the INTEN and INT0F Registers.

Figure 11.11

INTEN and INT0F Registers

INT0

_______

Input Filter Select Register

Symbol

Address

After Reset

INT0F

001Eh

00h

Bit Symbol

Bit Name

Function

INT0

_____

Input Filter Select Bit

INT0F0

INT0F1

b7 b6 b5 b4 b3 b2 b1 b0

Reserved Bit

Nothing is assigned. When w rite, set to “0”.

When read, its content is indeterminate.

b1 b0

0 0 : No filter

0 1 : Filter w ith f1 sampling

1 0 : Filter w ith f8 sampling

1 1 : Filter w ith f32 sampling

—

(b7-b3)

—

(b2)

Set to “0”

External Input Enable Register

Symbol

Address

After Reset

INTEN

0096h

00h

Bit Symbol

Bit Name

Function

INT0

_____

Input Enable Bit(1)

INT0

_____

Input Polarity Select Bit(2,3)

NOTES :

INT0EN

When setting the INT0PL bit to “1” (both edges), set the POL bit in the INT0IC register to “0” (selects falling

edge).

The IR bit in the INT0IC register may be set to “1” (requests interrupt) w hen the INT0PL bit is rew ritten. Refer to 20.2.5

Changing Interrupt Factor.

0 : Disable

1 : Enable

0 : One edge

1 : Both edges

Set to “0”

Reserved Bit

INT0PL

000

—

(b7-b2)

Set the INT0EN bit w hile the INOSTG bit in the PUM register is set to “0” (one-shot trigger disabled).

b3 b2 b1 b0

b7 b6 b5

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