R8CSLASH15 datasheet(49/277 Pages) RENESAS

49 / 277 page

R8C/14 Group, R8C/15 Group

8. Bus

Rev.2.10

Jan 19, 2006

Page 37 of 253

REJ09B0164-0210

Bus

During access, the ROM/RAM and SFR vary from bus cycles. Table 8.1 lists Bus Cycles for Access Space

of the R8C/14 Group and Table 8.2 lists Bus Cycles for Access Space of the R8C/15 Group.

The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word-(16 bits)

unit, these area are accessed twice in 8-bit unit. Table 8.3 lists Access Unit and Bus Operation.

Table 8.3

Access Unit and Bus Operation

Table 8.1

Bus Cycles for Access Space of the R8C/14 Group

Access Area

Bus Cycle

SFR

2 cycles of CPU clock

ROM/RAM

1 cycle of CPU clock

Table 8.2

Bus Cycles for Access Space of the R8C/15 Group

Access Area

Bus Cycle

SFR/Data flash

2 cycles of CPU clock

Program ROM/RAM

1 cycle of CPU clock

Area

SFR, Data flash

Even Address

Byte Access

ROM (Program ROM), RAM

Odd Address

Byte Access

Even Address

Word Access

Odd Address

Word Access

CPU Clock

Data

Even

Odd

Even+1

Even

Odd+1

Odd

Address

Even+1

Odd+1

Odd

Data

Even

Data

CPU Clock

Data

Address

CPU Clock

Data

Address

CPU Clock

Data

Address

Data

CPU Clock

Address

Data

CPU Clock

Address

Data

CPU Clock

Address

Data

CPU Clock

Address

Data

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