R8CSLASH15 datasheet(54/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

9. Clock Generation Circuit

Rev.2.10

Jan 19, 2006

Page 42 of 253

REJ09B0164-0210

Figure 9.4

OCD Register

Oscillation Stop Detection Register

(1)

Symbol

Address

After Reset

OCD

000Ch

04h

Bit Symbol

Bit Name

Function

NOTES :

The OCD3 bit remains “0” (main clock oscillates) if the OCD1 to OCD0 bits are set to “00b”.

The CM14 bit is set to “0” (low -speed on-chip oscillator on) if the OCD2 bit is set to “1” (selects on-chip oscillator

clock).

Refer to Figure 9.9 Procedure of Sw itching Clock Source From Low -Speed On-Chip Oscillator to Main

Clock for the sw itching procedure w hen the main clock re-oscillates after detecting an oscillation stop.

Set the PRC0 bit in the PRCR register to “1” (w rite enable) before rew riting to this register.

The OCD2 bit is automatically set to “1” (selects on-chip oscillator clock) if a main clock oscillation stop is detected

w hile the OCD1 to OCD0 bits are set to “11b” (oscillation stop detection function enabled). If the OCD3 bit is set to “1”

(main clock stops), the OCD2 bit remains unchanged w hen w riting “0” (selects main

clock).

The OCD3 bit is enabled w hen the OCD1 to OCD0 bits are set to “11b”.

Set the OCD1 to OCD0 bits to “00b” (oscillation stop detection function disabled) before entering stop and on-chip

oscillator mode (main clock stops).

—

(b7-b4)

Reserved Bit

Set to “0”

OCD3

Clock Monitor Bit(3,5)

0 : Main clock oscillates

1 : Main clock stops

OCD2

System Clock Select Bit(6)

0 : Selects main clock(7)

1 : Selects on-chip oscillator clock(2)

OCD1

Oscillation Stop Detection

Enable Bit

b1 b0

0 0 : Oscillation stop detection function

disabled

0 1 : Do not set

1 0 : Do not set

1 1 : Oscillation stop detection function

enabled(4,7)

OCD0

0000

b3 b2 b1 b0

b7 b6 b5 b4

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