R8CSLASH15 datasheet(73/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

11. Interrupt

Rev.2.10

Jan 19, 2006

Page 61 of 253

REJ09B0164-0210

11.1.6

Interrupt Control

The following describes enable/disable the maskable interrupts and set the priority order to

acknowledge. The contents explained does not apply to the nonmaskable interrupts.

Use the I flag in the FLG register, IPL and the ILVL2 to ILVL0 bits in each interrupt control register to

enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in

each interrupt control register.

Figure 11.3 shows the Interrupt Control Register and Figure 11.4 shows the INT0IC Register

Figure 11.3

Interrupt Control Register

(2)

Symbol

Address

After Reset

KUPIC

004Dh

XXXXX000b

ADIC

004Eh

XXXXX000b

SSUAIC

004Fh

XXXXX000b

CMP1IC

0050h

XXXXX000b

S0TIC

0051h

XXXXX000b

S0RIC

0052h

XXXXX000b

TXIC

0056h

XXXXX000b

TZIC

0058h

XXXXX000b

INT1IC

0059h

XXXXX000b

INT3IC

005Ah

XXXXX000b

TCIC

005Bh

XXXXX000b

CMP0IC

005Ch

XXXXX000b

Bit Symbol

Bit Name

Function

NOTES :

2. To rew rite the interrupt control register, rew rite it w hen the interrupt request w hich is applicable for its register is not

generated. Refer to 20.2.6 Changing Interrupt Control Registers.

b7 b6 b5 b4 b3 b2 b1 b0

ILVL0

Interrupt Priority Level Select Bit

b2 b1 b0

0 0 0 : Level 0 (interrupt disable)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL1

ILVL2

Interrupt Request Bit

0 : Requests no interrupt

1 : Requests interrupt

RW(1)

—

(b7-b4)

—

Nothing is assigned. When w rite, set to “0”.

When read, its content is indeterminate.

Only “0” can be w ritten to the IR bit. Do not w rite “ 1”.

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