R8CSLASH15 datasheet(93/277 Pages) RENESAS

93 / 277 page

R8C/14 Group, R8C/15 Group

12. Watchdog Timer

Rev.2.10

Jan 19, 2006

Page 81 of 253

REJ09B0164-0210

12.1

When Count Source Protection Mode Disabled

The count source of the watchdog timer is the CPU clock when count source protection mode is

disabled. Table 12.2 lists the Specification of Watchdog Timer (When Count Source Protection Mode is

Disabled).

NOTES:

1. The watchdog timer is reset when writing “00h” to the WDTR register before writing “FFh”. The

prescaler is reset after the microcomputer is reset. Some errors occur by the prescaler for the

period of the watchdog timer.

2. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write “0” to the bit

0 of the address 0FFFFh by a flash writer.

Table 12.2

Specification of Watchdog Timer (When Count Source Protection Mode is Disabled)

Item

Specification

Count Source

CPU clock

Count Operation

Decrement

Period

Division ratio of prescaler(n) x count value of watchdog timer(32768)(1)

CPU clock

n : 16 or 128 (selected by WDC7 bit in WDC register)

e.g.When the CPU clock is 16MHz and prescaler is divided by 16, the

period is approximately 32.8ms

Count Start Condition

The WDTON bit(2) in the OFS register (0FFFFh) selects the operation

of watchdog timer after reset

• When the WDTON bit is set to “1” (watchdog timer is in stop state

after reset)

The watchdog timer and prescaler stop after reset and the count

starts by writing to the WDTS register

• When the WDTON bit is set to “0” (watchdog timer starts

automatically after exiting )

The watchdog timer and prescaler start counting automatically after

reset

Reset Condition of Watchdog

Timer

• Reset

• Write “00h” to the WDTR register before writing “FFh”

• Underflow

Count Stop Condition

Stop and wait modes (inherit the count from the held value after exiting

modes)

Operation at the time of

Underflow

• When the PM12 bit in the PM1 register is set to “0”

Watchdog timer interrupt

• When the PM12 bit in the PM1 register is set to “1”

Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)

R8C/15 Datasheet(PDF) 93 Page - Renesas Technology Corp

R8C/15 Datasheet(HTML) 93 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL