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R8C/15 Datasheet(PDF) 46 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 46 Page - Renesas Technology Corp |
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46 / 277 page  R8C/14 Group, R8C/15 Group 6. Voltage Detection Circuit Rev.2.10 Jan 19, 2006 Page 34 of 253 REJ09B0164-0210 Figure 6.8 Operating Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Vdet2 (Typ. 3.30V) VCA13 Bit Internal Reset Signal (VW2C6=1) VCC The above applies to the following conditions. • VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled) • VW2C0 bit in VW2C register = 1 (enables voltage monitor 2 interrupt and voltage monitor 2 reset) NOTES: 1. When the voltage monitor 1 reset is not used, set the power supply to VCC ≥ 2.7. 2.7V(1) “0” “1” Sampling Clock of Digital Filter x 4 Cycles VW2C2 Bit “0” “1” When the VW2C1 bit is set to “0” (digital filter enabled) VW2C2 Bit “0” “1” When the VW2C1 bit is set to “1” (digital filter disabled) and the VW2C7 bit is set to “0” (Vdet2 or above) VCA13 : Bit in VCA1 Register VW2C1, VW2C2, VW2C6, VW2C7 : Bit in VW2C Register Set to “0” by interrupt request acknowledgement Set to “0” by a program Voltage Monitor 2 Interrupt Request (VW2C6=0) Voltage Monitor 2 Interrupt Request (VW2C6=0) VW2C2 Bit “0” “1” When the VW2C1 bit is set to “1” (digital filter disabled) and the VW2C7 bit is set to “1” (Vdet2 or below) Voltage Monitor 2 Interrupt Request (VW2C6=0) Internal Reset Signal (VW2C6=1) Sampling Clock of Digital Filter x 4 Cycles Set to “0” by a program Set to “0” by interrupt request acknowledgement Set to “0” by a program Set to “0” by interrupt request acknowledgement |
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