R8CSLASH15 datasheet(42/277 Pages) RENESAS

42 / 277 page

R8C/14 Group, R8C/15 Group

6. Voltage Detection Circuit

Rev.2.10

Jan 19, 2006

Page 30 of 253

REJ09B0164-0210

Figure 6.6

VW2C Register

Voltage Monitor 2 Circuit Control Register

(1)

Symbol

Address

After Reset(8)

VW2C

0037h

00h

Bit Symbol

Bit Name

Function

NOTES :

10. Set the VW2C0 bit to “0” (disabled) under the conditions of the VCA13 bit in the VCA1 register set to “1” (VCC

≥

Vdet2 or voltage detection 2 circuit disabled), the VW2C1 bit set to “1” (digital filter disabled mode) and the VW2C7

bit set to “0” (w hen VCC reaches Vdet2 or above).

Set the VW2C0 bit to “0” (disabled) under the conditions of the VCA13 bit set to “0” (VCC < Vdet2), the VW2C1 bit

set to “1” (digital filter disabled mode) and the VW2C7 bit set to “1” (w hen VCC reaches Vdet2 or below ).

0 : Not detected

1 : Vdet2 pass detected

b1 b0

b7 b6 b5 b4 b3

VW2C0

Voltage Monitor 2 Interrupt /

Reset Enable Bit(6, 10)

0 : Disable

1 : Enable

0 : Digital filter enabled mode

(digital filter circuit enabled)

1 : Digital filter disabled mode

(digital filter circuit disabled)

VW2C2

Voltage Change Detection

Flag(3,4,8)

VW2C1

Voltage Monitor 2 Digital Filter

Disable Mode Select Bit(2)

VW2C3

WDT Detection Flag(4,8)

VW2F1

Sampling Clock Select Bit

b5 b4

0 0 : fRING-S divide-by-1

0 1 : fRING-S divide-by-2

1 0 : fRING-S divide-by-4

1 1 : fRING-S divide-by-8

VW2F0

0 : Not detected

1 : Detected

VW2C6

Voltage Monitor 2 Circuit Mode

Select Bit(5)

0 : Voltage monitor 2 interrupt mode

1 : Voltage monitor 2 reset mode

VW2C7

Voltage Monitor 2 Interrupt /

Reset Generation Condition

Select Bit(7,9)

0 : When VCC reaches Vdet2 or above

1 : When VCC reaches Vdet2 or below

When the VW2C6 bit is set to “1” (voltage monitor 2 reset mode), set the VW2C7 bit to “1” (w hen VCC

reaches to Vdet2 or below )(do not set to “0”).

Set the PRC3 bit in the PRCR register to “1” (rew rite enable) before w riting to this register.

When rew riting the VW2C register, the VW2C2 bit may be set to “1”. Set the VW2C2 bit to “0” after rew riting the

VW2C register.

When the voltage monitor 2 interrupt is used to exit stop mode and to return again, w rite “0” to the VW2C1

bit before w riting “1”.

This bit is enabled w hen the VCA27 bit in the VCA2 register is set to “1” (voltage detection 2 circuit

enabled).

Set this bit to “0” by a program. When w riting “0” by a program, it is set to “0” (It remains unchanged even if it is set

to “1”).

This bit is enabled w hen the VW2C0 bit is set to “1” (voltage monitor 2 interrupt / enables reset).

The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to “1” (voltage detection 2 circuit

enabled). Set the VW2C0 bit to “0” (disable) w hen the VCA27 bit is set to “0” (voltage detection 2 circuit disabled).

The VW2C7 bit is enabled w hen the VW2C1 bit is set to “1” (digital filter disabled mode).

The VW2C2 and VW2C3 bits remain unchanged in the softw are reset, w atchdog timer reset and voltage monitor 2

reset.

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