R8CSLASH15 datasheet(52/277 Pages) RENESAS

52 / 277 page

R8C/14 Group, R8C/15 Group

9. Clock Generation Circuit

Rev.2.10

Jan 19, 2006

Page 40 of 253

REJ09B0164-0210

Figure 9.2

CM0 Register

System Clock Control Register 0

(1)

Symbol

Address

After Reset

CM0

0006h

68h

Bit Symbol

Bit Name

Function

NOTES :

b7 b6 b5 b4 b3 b2 b1 b0

00 1

0 0

—

(b1-b0)

Reserved Bit

Set to “0”

CM02

WAIT Peripheral Function Clock Stop

Bit

0 : Peripheral function clock does not

stop in w ait mode

1 : Peripheral function clock stops

in w ait mode

—

(b3)

Reserved Bit

Set to “1”

—

(b4)

Reserved Bit

Set to “0”

CM05

Main Clock (XIN-XOUT)

Stop Bit(2,4)

0 : Main clock oscillates

1 : Main clock stops(3)

CM06

System Clock Division Select Bit 0(5)

0 : Enables CM16, CM17

1 : Divide-by-8 mode

—

(b7)

Reserved Bit

Set to “0”

When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).

Set the PRC0 bit in the PRCR register to “1” (w rite enable) before rew riting to this register.

The CM05 bit is to stop the main clock w hen the on-chip oscillator mode is selected.

Do not use this bit for w hether the main clock is stopped. To stop the main clock, set the bits in the follow ing

orders:

(a) Set the OCD1 to OCD0 bits in the OCD register to “00b” (oscillation stop detection function disabled).

(b) Set the OCD2 bit to “1” (selects on-chip oscillator clock).

Set the CM05 bit to “1” (main clock stops) and the CM13 bit in the CM1 register to “1”

(XIN-XOUT pin) w hen the external clock is input.

When the CM05 bit is set to “1” (stops main clock), P4_6 and P4_7 can be used as input ports.

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