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R8C/15 Datasheet(PDF) 48 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 277 page  R8C/14 Group, R8C/15 Group 7. Processor Mode Rev.2.10 Jan 19, 2006 Page 36 of 253 REJ09B0164-0210 Figure 7.2 PM1 Register Processor Mode Register 1 (1) Symbol Address After Reset PM1 0005h 00h Bit Symbol Bit Name Function RW NOTES : 1. 2. Reserved Bit Set to “0” — (b0) 0 : Watchdog Timer Interrupt 1 : Watchdog Timer Reset(2) RW b7 b6 b5 b4 0 — (b1) RW — (b7) RW b3 b2 — b1 b0 0 — The PM12 bit is set to “1” by a program (It remains unchanged even if it is set to “0”). When the CSPRO bit in the CSPR register is set to “1” (selects count source protect mode), the PM12 bit is automatically set to “1”. Reserved Bit Set to “0” Nothing is assigned. When w rite, set to “0”. When read, its content is indeterminate. Set the PRC1 bit in the PRCR register to “1” (w rite enable) before rew riting to this register. — (b6-b3) PM12 WDT Interrupt/Reset Sw itch Bit Nothing is assigned. When w rite, set to “0”. When read, its content is “0”. |
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