R8CSLASH15 datasheet(76/277 Pages) RENESAS

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R8C/14 Group, R8C/15 Group

11. Interrupt

Rev.2.10

Jan 19, 2006

Page 64 of 253

REJ09B0164-0210

11.1.6.4

Interrupt Sequence

An interrupt sequence is performed between an interrupt request acknowledgement and interrupt

routine execution.

When an interrupt request is generated while an instruction is executed, the CPU determines its

interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from

the following cycle. However, in regards to the SMOVB, SMOVF, SSTR or RMPA instruction, if an

interrupt request is generated while executing the instruction, the microcomputer suspends the

instruction to start the interrupt sequence. The interrupt sequence is performed as follows. Figure

11.5 shows the Time Required for Executing Interrupt Sequence.

(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading

the address 00000h. The IR bit for the corresponding interrupt is set to “0” (interrupt not

requested).

(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU

internal temporary register(1).

(3) The I, D and U flags in the FLG register are set as follows:

The I flag is set to “0” (disables interrupts).

The D flag is set to “0” (disables single-step interrupt).

The U flag is set to “0” (ISP selected).

However, the U flag does not change state if an INT instruction for software interrupt numbers

32 to 63 is executed.

(4) The CPU’s internal temporary register(1) is saved to the stack.

(5) The PC is saved to the stack.

(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.

(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, the instructions are executed from the starting address of

the interrupt routine.

NOTES:

1. This register cannot be used by user.

Figure 11.5

Time Required for Executing Interrupt Sequence

678

CPU Clock

Address Bus

Data Bus

Address

0000h

Indeterminate

Interrupt

information

SP-2 SP-1

SP-4

SP-3

VEC

VEC+1

VEC+2

SP-2

contents

SP-1

contents

SP-4

contents

SP-3

contents

VEC

contents

VEC+1

contents

VEC+2

contents

The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is

ready to acknowledge instructions.

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