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R8C/15 Datasheet(PDF) 191 Page - Renesas Technology Corp |
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R8C/15 Datasheet(HTML) 191 Page - Renesas Technology Corp |
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191 / 277 page ![]() R8C/14 Group, R8C/15 Group 17. Programmable I/O Ports Rev.2.10 Jan 19, 2006 Page 179 of 253 REJ09B0164-0210 17. Programmable I/O Ports Programmable Input/Output ports (hereafter referred to as “I/O ports”) have 13 ports of the P1, P3_3 to P3_5, P3_7, and P4_5. Also, the main clock oscillation circuit is not used, the P4_6 and P4_7 can be used as the input port only. Table 17.1 lists the Overview of Programmable I/O Ports. NOTES: 1. In input mode, whether the internal pull-up resistor is connected or not can be selected by the PUR0 and PUR1 registers. 2. This port can be used as the LED drive port by setting the DRR register to “1” (High). 3. When the main clock oscillation circuit is not used, these ports can be used as the input port only. 17.1 Functions of Programmable I/O Ports The PDi_j (j=0 to 7) bit in the PDi (i=1,3 and 4) register controls I/O of the ports P1, P3_3 to P3_5, P3_7 and P4_5. The Pi register consists of a port latch to hold output data and a circuit to read pin state. Figures 17.1 to 17.3 show the Configurations of Programmable I/O Ports. Table 17.2 lists the Functions of Programmable I/O Ports. Also, Figure 17.5 shows the PD1, PD3 and PD4 Registers. Figure 17.6 shows the P1, P3 and P4 Registers, Figure 17.7 shows the PUR0 and PUR1 Registers and Figure 17.8 shows the DRR Register. NOTES: 1. Nothing is assigned to the PD3_0 to PD3_2, PD3_6, PD4_0 to PD4_4, PD4_6 and PD4_7 bits. 17.2 Effect on Peripheral Functions Programmable I/O ports function as I/O of peripheral functions (Refer to Table 1.6 Pin Name Information by Pin Number). Table 17.3 lists the Setting of PDi_j Bit When Functioning as I/O of Peripheral Functions. Refer to descriptions of each function for how to set peripheral functions. 17.3 Pins Other than Programmable I/O Ports Figure 17.4 shows the Configuration of I/O Pins. Table 17.1 Overview of Programmable I/O Ports Ports I/O Output Form I/O Setting Internal Pull-Up Resistor Drive Capacity Selection P1 I/O CMOS3 State Set every bit Set every 4 bits(1) Set every bit(2) of P1_0 to P1_3 P3_3, P4_5 I/O CMOS3 State Set every bit Set every bit(1) None P3_4, P3_5, P3_7 I/O CMOS3 State Set every bit Set every 3 bits(1) None P4_6, P4_7(3) I (Without output function) None None None Table 17.2 Functions of Programmable I/O Ports Operation When Accessing Pi Register Value of PDi_j Bit in PDi Register(1) When PDi_j bit is set to “0” (input mode) When PDi_j bit is set to “1” (output mode) Reading Read pin input level Read the port latch Writing Write to the port latch Write to the port latch. The value written in the port latch, it is output from the pin. Table 17.3 Setting of PDi_j Bit When Functioning as I/O of Peripheral Functions I/O of Peripheral Functions PDi_j Bit Setting of Port shared with Pin Input Set this bit to “0” (input mode). Output This bit can be set to both “0” and “1” (output regardless of the port setting) |
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