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4501 Datasheet(PDF) 120 Page - Renesas Technology Corp

Part # 4501
Description  4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES
PDF  212 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

4501 Datasheet(HTML) 120 Page - Renesas Technology Corp

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2.1 I/O pins
2-3
4501 Group
APPLICATION
Rev.2.01
Feb 07, 2005
REJ09B0192-0201
(3)
Port P2
Port P2 is a 2-bit I/O port.
Also, its key-on wakeup function is switched to ON/OFF by the register K20 and K21, and its pull-
up transistor function is switched to ON/OFF by the register PU20 and PU21.
s Input/output of port P2
q Data input to port P2
Set the output latch of specified port P2i (i=0, 1) to “1” with the OP2A instruction. If the output
latch is set to “0,” “L” level is input.
The state of port P2 is transferred to register A when the IAP2 instruction is executed.
However, port P2 is 2 bits and A2 and A3 are fixed to “0.”
q Data output from port P2
The contents of register A is output to port P2 with the OP2A instruction.
The output structure is an N-channel open-drain.
(4)
Port D
D0–D3 are four independent I/O ports.
Also, as for ports D2 and D3, its key-on wakeup function is switched to ON/OFF by the register K22
and K23, and its pull-up transistor function is switched to ON/OFF by the register PU22 and PU23.
s Input/output of port D
Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0–D3, select one
of port D with the register Y of the data pointer first.
q Data input to port D
Set the output latch of specified port Di (i = 0 to 3) to “1” with the SD instruction.
When the output latch is set to “0,” “L” level is input.
When the SZD instruction is executed, if the port specified by register Y is “0,” the next
instruction is skipped. If it is “1,” the next instruction is executed.
q Data output from port D
Set the output level to the output latch with the SD and RD instructions.
The state of pin enters the high-impedance state when the SD instruction is executed.
The states of all port D enter the high-impedance state when the CLD instruction is executed.
The state of pin becomes “L” level when the RD instruction is executed.
The output structure is an N-channel open-drain.
Notes 1: When the SD and RD instructions are used, do not set “01002” or more to register Y.
2: Port D2 is also used as Port C. Accordingly, when using port D2, set the output latch to
“1” with the SCP instruction.
3: Port D3 is also used as Port K. Accordingly, when using port D3, set the output latch to
“1” with the OKA instruction.



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