4501 datasheet(122/212 Pages) RENESAS

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2.1 I/O pins

2-5

4501 Group

APPLICATION

Rev.2.01

Feb 07, 2005

REJ09B0192-0201

Pull-up control register PU0

at reset : 00002

at RAM back-up : state retained

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Port P03

pull-up transistor control bit

Port P02

pull-up transistor control bit

Port P01

pull-up transistor control bit

Port P00

pull-up transistor control bit

PU03

PU02

PU01

PU00

Note: “W” represents write enabled.

2.1.2 Related registers

(1)

Key-on wakeup control register K0

Set the contents of this register through register A with the TK0A instruction.

The contents of register K0 is transferred to register A with the TAK0 instruction.

Table 2.1.1 shows the key-on wakeup control register K0.

Table 2.1.1 Key-on wakeup control register K0

Key-on wakeup control register K0

at reset : 00002

at RAM back-up : state retained

R/W

Key-on wakeup invalid

Key-on wakeup valid

Key-on wakeup invalid

Key-on wakeup valid

Key-on wakeup invalid

Key-on wakeup valid

Key-on wakeup invalid

Key-on wakeup valid

Port P03

key-on wakeup control bit

Port P02

key-on wakeup control bit

Port P01

key-on wakeup control bit

Port P00

key-on wakeup control bit

K03

K02

K01

K00

Note: “R” represents read enabled, and “W” represents write enabled.

(2)

Pull-up control register PU0

Set the contents of this register through register A with the TPU0A instruction.

Table 2.1.2 shows the pull-up control register PU0.

Table 2.1.2 Pull-up control register PU0

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