4501 datasheet(134/212 Pages) RENESAS

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2.2 Interrupts

2-17

4501 Group

APPLICATION

Rev.2.01

Feb 07, 2005

REJ09B0192-0201

Fig. 2.2.2 INT interrupt setting example

Note: The valid waveforms causing the interrupt must be retained at their level for 4 cycles or more

of system clock.

➁ Set Port

Port used for INT interrupt is set to input port.

b3b0

✕✕ Both edges detection selected (TI1A instruction)

b3b0

➀ Disable Interrupts

INT interrupt is temporarily disabled.

Interrupt enable flag INTE

Interrupt control register V1

Interrupt enable flag INTE

“0”

✕✕ ✕

All interrupts disabled (DI instruction)

INT interrupt occurrence disabled

(TV1A instruction)

Port P13 output latch

✕✕

Set to input (OP1A instruction)

➂ Set Valid Waveform

Valid waveform of INT pin is selected.

Both edges detection selected

Interrupt control register I1

➄ Clear Interrupt Request

INT interrupt activated condition is cleared.

INT interrupt request flag EXF0

“0”

INT interrupt activated condition cleared

(SNZ0 instruction)

Note when the interrupt request is cleared

When ➄ is executed, considering the skip of the next instruction according to the

interrupt request flag EXF0, insert the NOP instruction after the SNZ0 instruction.

➅ Enable Interrupts

The INT interrupt which is temporarily disabled is enabled.

“1”

✕✕ ✕

INT interrupt occurrence enabled

(TV1A instruction)

All interrupts enabled (EI instruction)

INT interrupt execution started

“✕”: it can be “0” or “1.”

➃ Execute NOP Instruction

NOP instruction

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