4501 datasheet(132/212 Pages) RENESAS

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2.2 Interrupts

2-15

4501 Group

APPLICATION

Rev.2.01

Feb 07, 2005

REJ09B0192-0201

Interrupt control register I1

at reset : 00002

at RAM back-up : state retained

R/W

INT pin input disabled

INT pin input enabled

Falling waveform (“L” level of INT pin is recognized with

the SNZI0 instruction)/“L” level

Rising waveform (“H” level of INT pin is recognized with

the SNZI0 instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

INT pin input control bit (Note 2)

Interrupt valid waveform for INT

pin/return level selection bit

(Note 2)

INT pin edge detection circuit

control bit

INT pin

timer 1 control enable bit

I13

I12

I11

I10

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be

set. Accordingly, clear EXF0 flag with the SNZ0 instruction when the bit 0 (V10) of register V1 to

“0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is

performed with the SNZ0 instruction.

(5)

Interrupt control register I1

The INT pin timer 1 control enable bit is assigned to bit 0, INT pin edge detection circuit control bit

is assigned to bit 1, interrupt valid waveform for INT pin/return level selection bit is assigned to bit

2 and INT pin input control bit is assigned to bit 3.

Set the contents of this register through register A with the TI1A instruction.

In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.

Table 2.2.3 shows the interrupt control register I1.

Table 2.2.3 Interrupt control register I1

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