4501 datasheet(162/212 Pages) RENESAS

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2.7 RAM back-up

2-45

4501 Group

APPLICATION

Rev.2.01

Feb 07, 2005

REJ09B0192-0201

Pull-up control register PU0

at reset : 00002

at RAM back-up : state retained

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Port P03

pull-up transistor control bit

Port P02

pull-up transistor control bit

Port P01

pull-up transistor control bit

Port P00

pull-up transistor control bit

PU03

PU02

PU01

PU00

Note: “W” represents write enabled.

(4)

Pull-up control register PU0

Set the contents of this register through register A with the TPU0A instruction.

Table 2.7.7 shows the pull-up control register PU0.

Table 2.7.7 Pull-up control register PU0

(3)

Key-on wakeup control register K2

Set the contents of this register through register A with the TK2A instruction.

The contents of register K2 is transferred to register A with the TAK2 instruction.

Table 2.7.6 shows the key-on wakeup control register K2.

Table 2.7.6 Key-on wakeup control register K2

Key-on wakeup control register K2

at reset : 00002

at RAM back-up : state retained

R/W

Key-on wakeup invalid

Key-on wakeup valid

Key-on wakeup invalid

Key-on wakeup valid

Key-on wakeup invalid

Key-on wakeup valid

Key-on wakeup invalid

Key-on wakeup valid

Port D3/K

key-on wakeup control bit

Port D2/C

key-on wakeup control bit

Port P21/AIN1

key-on wakeup control bit

Port P20/AIN0

key-on wakeup control bit

K23

K22

K21

K20

Note: “R” represents read enabled, and “W” represents write enabled.

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