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PCM5310PAP Datasheet(PDF) 65 Page - Texas Instruments |
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PCM5310PAP Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 103 page ![]() Register 56 (38h) PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 56 38h Power up/down, oversampling rate control for DAC34 PD34 RSV OV34[1:0] ZR34 RSV RSV RSV PD34: Power Up/Down Control for DAC34 This bit controls the power up/down for DAC34, including the interpolation filter. Default value: 1 0 Power up 1 Power down (default) OV34[1:0]: Oversampling Rate Control for DAC34 These bits control the oversampling rate of the DAC34 delta-sigma modulator. Default value: 01 SYSTEM CLOCK RATE OV34 128 fS, 192 fS 256 fS, 384 fS 128 fS, 192 fS 00 16 fS 32 fS 64 fS 01 (default) 32 fS 64 fS 128 fS 10 — — 11 32 fS 128 fS (1) 128 fS (1) (1) Less than fS = 48 kHz ZR34: Zero Flag Reverse This bit reverses the polarity of the zero flag output. The zero flag is high after input data are zero during 1024 fS when ZR34 = '0', and is set with the GPIO port by bits GSL1[4:0], GSL2[4:0], GSL3[4:0] in registers 09 to 11. Default value: 0 0 Buffered output (default) 1 Inverted output Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 65 Product Folder Link(s): PCM5310 |
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