PCM5310PAP datasheet(19/103 Pages) TI

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SYSTEM CLOCK INPUT, OUTPUT, AND fS AUTOMATIC DETECTION

SCK1to6

Low

High

0.8V

2.0V

SCL

SCH

SCY

PCM5310

www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009

The PCM5310 has six system clock input ports: SCK1, SCK2, SCK3, SCK4, SCK5, and SCK6. Each input port

can receive an independent clock at various frequencies. These ports are used for the internal clock of the digital

filters and delta-sigma modulators, which are combined into a single common audio clock. The PCM5310

automatically detects the input clock rate at 128 fS, 192 fS, 256 fS, 384 fS, 512 fS or 768 fS (where fS is the audio

sampling rate); if necessary, automatic clock rate detection can be disabled. The descriptions for the system

clock input, output, and fS automatic detection registers are shown in Table 3. Table 4 shows the frequency of

the common audio clock. Figure 30 and Table 5 shows the timing requirements for the system clock input.

Table 3. System Clock Input, Output, and fS Automatic Detection Registers

Master or slave with fS detection for DAC12

DMS12[3:0]

Audio interface format for DAC12

DFM12[1:0]

Master or slave with fS detection for DAC34

DMS34[3:0]

Audio interface format for DAC34

DFM34[1:0]

Master or slave with fS detection for ADC12

AMS12[3:0]

Audio interface format for ADC12

AFM12[1:0]

Master or slave with fS detection for ADC34

AMS34[3:0]

Audio interface format for ADC34

AFM34[1:0]

SCK6 clock output selection

PSC6[2:0]

Table 4. System Clock Frequencies for the Common Audio Clock

SAMPLING

SYSTEM CLOCK FREQUENCY (MHz)

FREQUENCY

(kHz)

128 fS

(1)

192 fS

(1)

256 fS

384 fS

512 fS

768 fS

4.0960

6.1440

8.1920

12.2880

16.3840

24.5760

44.1

5.6488

8.4672

11.2896

16.9344

22.5792

33.8688

6.1440

9.2160

12.2880

18.4320

24.5760

36.8640

88.2

11.2896

16.9344

22.5792

33.8688

Not supported

12.2880

18.4320

24.5760

36.8640

Not supported

176.4(1)

22.5792

33.8688

Not supported

192(1)

24.5760

36.8640

Not supported

(1)

This sampling frequency and system clock frequency are supported only for the DAC.

Figure 30. System Clock Input Timing

Table 5. Timing Characteristics for Figure 30

PARAMETER

MIN

MAX

UNIT

tSCY

System clock cycle time

tSCH

System clock high time

0.4 tSCY

tSCL

System clock low time

0.4 tSCY

System clock duty cycle

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