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PCM5310PAP Datasheet(PDF) 69 Page - Texas Instruments |
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PCM5310PAP Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 103 page ![]() Register 84 (54h) PCM5310 www.ti.com ............................................................................................................................................................................................ SLES244 – FEBRUARY 2009 REG HEX DESCRIPTION B7 B6 B5 B4 B3 B2 B1 B0 84 54h Master/slave interface format for ADC12 AMS12[3:0] HF12 RSV AFM12[1:0] AMS12[3:0]: Master/Slave Audio Interface Setting for ADC12 These bits set the master or slave mode. ADC12 receives LRCK and BCK from PORT-1, PORT-2, PORT-3, PORT-4, PORT-5 or PORT-6 in slave mode, and generates LRCK and BCK from SCK in master mode. Default value: 1000 MASTER/SLAVE AUDIO INTERFACE SETTING FOR MASTER/SLAVE AUDIO INTERFACE SETTING FOR AMS12[3:0] ADC12 AMS12[3:0] ADC12 0000 Reserved 1000 Slave and system clock fS auto-detect mode (default) 0001 Master and system clock 768 fS 1001 Slave and system clock 768 fS 0010 Master and system clock 512 fS 1010 Slave and system clock 512 fS 0011 Master and system clock 384 fS 1011 Slave and system clock 384 fS 0100 Master and system clock 256 fS 1100 Slave and system clock 256 fS 0101 Reserved 1101 Reserved 0110 Reserved 1110 Reserved 0111 Reserved 1111 Reserved HF12: High-Pass Filter Disable for ADC12 This bit disables the digital high-pass filter of ADC12. Default value: 0 0 (0.019 fS/1000) Hz (default) 1 Off AFM12[1:0]: Audio Interface Format for ADC12 These bits select the ADC12 audio data format as I2S, right-justified, or left-justified. Default value: 00 00 16 to 24 bits, I2S (default) 01 16 to 24 bits, left-justified 10 24 bits, right-justified 11 16 bits, right-justified Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 69 Product Folder Link(s): PCM5310 |
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