 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320VC5504 Datasheet(PDF) 122 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMS320VC5504 Datasheet(HTML) 122 Page - Texas Instruments |
|
|
122 / 128 page  6.18.3 GPIO Peripheral Input Latency Electrical Data/Timing TMS320VC5504 Fixed-Point Digital Signal Processor SPRS609A – JUNE 2009 – REVISED JULY 2009 www.ti.com Table 6-46. Timing Requirements for GPIO Input Latency(1) CVDD = 1.05 V NO CVDD = 1.3 V UNIT . MIN MAX Polling GPIO_DIN register 5 cyc 1 tL(GPI) Latency, GP[x] input Polling GPIO_IFR register 7 cyc Interrupt Detection 8 cyc (1) The pulse width given is sufficient to generate a CPU interrupt. However, if a user wants to have VC5504 recognize the GP[x] input changes through software polling of the GPIO register, the GP[x] input duration must be extended to allow device enough time to access the GPIO register through the internal bus. Peripheral Information and Electrical Specifications 122 Submit Documentation Feedback |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
