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TMS320VC5504 Datasheet(PDF) 121 Page - Texas Instruments |
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TMS320VC5504 Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 128 page ![]() 6.18.2 GPIO Peripheral Input/Output Electrical Data/Timing GP[x] Input (With IOINTEDGy = 0) 4 3 2 1 GP[x] Output GP[x] Input (With IOINTEDGy = 1) 2 1 TMS320VC5504 Fixed-Point Digital Signal Processor www.ti.com SPRS609A – JUNE 2009 – REVISED JULY 2009 Table 6-44. Timing Requirements for GPIO Inputs(1) (see Figure 6-31) CVDD = 1.05 V CVDD = 1.3 V NO. UNIT MIN MAX 1 tw(ACTIVE) Pulse duration, GPIO input/external interrupt pulse active 2C(1)(2) ns 2 tw(INACTIVE) Pulse duration, GPIO input/external interrupt pulse inactive C (1)(2) ns (1) The pulse width given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration must be extended to allow the device enough time to access the GPIO register through the internal bus. (2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns. Table 6-45. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 6-31) CVDD = 1.05 V CVDD = 1.3 V NO. PARAMETER UNIT MIN MAX 3 tw(GPOH) Pulse duration, GP[x] output high 3C(1)(2) ns 4 tw(GPOL) Pulse duration, GP[x] output low 3C(1)(2) ns (1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO is dependent upon internal bus activity. (2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns. Figure 6-31. GPIO Port Timing Submit Documentation Feedback Peripheral Information and Electrical Specifications 121 |
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