ATtiny48 datasheet(110/266 Pages) ATMEL

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110

8008C–AVR–03/09

ATtiny48/88

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (see “Interrupts” on page 47) is executed when the ICF1 Flag, located in TIFR1, is set.

• Bit 4, 3 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 47) is executed when the OCF1B Flag, located in

TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 47) is executed when the OCF1A Flag, located in

TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector

(See “Watchdog Timer” on page 42.) is executed when the TOV1 Flag, located in TIFR1, is set.

12.11.9

TIFR1 – Timer/Counter1 Interrupt Flag Register

• Bit 7, 6 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the coun-

ter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

• Bit 4, 3 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

Bit

654

–

ICF1

–

OCF1B

OCF1A

TOV1

TIFR1

Read/Write

R/W

Initial Value

ATtiny48 Datasheet(PDF) 110 Page - ATMEL Corporation

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