ATtiny48 datasheet(112/266 Pages) ATMEL

112 / 266 page

112

8008C–AVR–03/09

ATtiny48/88

13. Timer/Counter0 and Timer/Counter1 Prescalers

“8-bit Timer/Counter0” on page 75 and “16-bit Timer/Counter1 with PWM” on page 84 share the

same prescaler module, but the Timer/Counters can have different prescaler settings. The

description below applies to both Timer/Counter1 and Timer/Counter0.

13.1

Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (f

CLK_I/O). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f

CLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or

CLK_I/O/1024.

13.2

Prescaler Reset

The prescaler is free running, i.e., operates independently of the Clock Select logic of the

Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is

not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications

for situations where a prescaled clock is used. One example of prescaling artifacts occurs when

the timer is enabled and clocked by the prescaler (CSn2:0 = 0b010, 0b011, 0b100, or 0b101).

The number of system clock cycles from when the timer is enabled to the first count occurs can

be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or

1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-

tion. However, care must be taken if the other Timer/Counter that shares the same prescaler

also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is

connected to.

13.3

External Clock Source

An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock

(clk

T1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization

logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1

shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector

logic. The registers are clocked at the positive edge of the internal system clock (clk

I/O). The latch

is transparent in the high period of the internal system clock.

The edge detector generates one clk

T1/clkT0 pulse for each positive (CSn2:0 = 7) or negative

(CSn2:0 = 6) edge it detects.

Figure 13-1. T1/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T1/T0 pin to the counter is updated.

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

clk

I/O

ATtiny48 Datasheet(PDF) 112 Page - ATMEL Corporation

ATtiny48 Datasheet(HTML) 112 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL