ATtiny48 datasheet(121/266 Pages) ATMEL

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121

8008C–AVR–03/09

ATtiny48/88

Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient

time for data signals to stabilize. This is clearly seen by summarizing Table 14-3 on page 121

and Table 14-4 on page 122, as done in Table 14-2 below.

14.5

14.5.1

SPCR – SPI Control Register

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 14-3 and Figure 14-4 for an example. The CPOL functionality is sum-

marized below:

Table 14-2.

Setting SPI Mode using Control Bits CPOL and CPHA

CPOL

CPHA

SPI Mode

Leading Edge

Trailing eDge

Sample (Rising)

Setup (Falling)

Setup (Rising)

Sample (Falling)

Setup (Rising)

Setup (Falling)

Sample (Rising)

Bit

654

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

SPCR

Read/Write

R/W

Initial Value

Table 14-3.

CPOL Functionality

CPOL

Leading Edge

Trailing Edge

Rising

Falling

Rising

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