ATtiny48 datasheet(130/266 Pages) ATMEL

130 / 266 page

130

8008C–AVR–03/09

ATtiny48/88

15.5

Overview of the TWI Module

The TWI module is comprised of several submodules, as shown in Figure 15-9. All registers

drawn in a thick line are accessible through the AVR data bus.

Figure 15-9. Overview of the TWI Module

15.5.1

SCL and SDA Pins

These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a

slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike

suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR

pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as

explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need

for external ones.

15.5.2

Bit Rate Generator Unit

When operating in a Master mode this unit controls the period of SCL. The SCL period is con-

trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status

clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that

slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.

Address Register

(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register

(TWCR)

Status Register

(TWSR)

State Machine and

Status control

SCL

Slew-rate

Control

Spike

Filter

SDA

Slew-rate

Control

Spike

Filter

Bit Rate Generator

Bit Rate Register

(TWBR)

Prescaler

Bus Interface Unit

START / STOP

Control

Arbitration detection

Ack

Spike Suppression

Address/Data Shift

ATtiny48 Datasheet(PDF) 130 Page - ATMEL Corporation

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