ATtiny48 datasheet(131/266 Pages) ATMEL

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8008C–AVR–03/09

ATtiny48/88

The TWI can be set to operate in high-speed mode, as described in “TWHSR – TWI High Speed

mode it relies on a prescaled version of the same. Depending on the clock signal used, the SCL

frequency is generated according to one of the following equations.

In normal mode:

In high-speed mode:

...where:

•clk

I/O = prescaled system clock, see Figure 6-1 on page 25

•clk

TWIHS = system clock, see Figure 6-1 on page 25

• TWBR = value of TWI Bit Rate Register, see “TWBR – TWI Bit Rate Register” on page 151

• TWPS = value of TWI prescaler, see Table 15-7 on page 153

Note:

In TWI Master mode TWBR must be 10, or higher .

15.5.3

Bus Interface Unit

This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and

Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,

or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also

contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-

ter is not directly accessible by the application software. However, when receiving, it can be set

or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the

value of the received (N)ACK bit can be determined by the value in the TWSR.

The START/STOP Controller is responsible for generation and detection of START, REPEATED

START, and STOP conditions. The START/STOP controller is able to detect START and STOP

conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up

if addressed by a Master.

If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-

ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost

an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate

status codes generated.

15.5.4

Address Match Unit

The Address Match unit checks if received address bytes match the seven-bit address in the

TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the

TWAR is written to one, all incoming address bits will also be compared against the General Call

address. Upon an address match, the Control Unit is informed, allowing correct action to be

taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.

The Address Match unit is able to compare addresses even when the AVR MCU is in sleep

SCL

clk

I/O

TWBR

TWPS

()

--------------------------------------------------------------------

SCL

clk

TWIHS

TWBR

TWPS

()

--------------------------------------------------------------------

ATtiny48 Datasheet(PDF) 131 Page - ATMEL Corporation

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