FX980 datasheet(43/86 Pages) CMLMICRO

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TETRA Baseband Processor

FX980

D/980/3

RxErrorStatus

Title:

Receive Error Status register.

Address:

$0x20

Function:

Description:

This register is the Rx Data path error status register. The RxIrqActive bit is set active when one

of the other bits in this register is the source of an interrupt event. All these error conditions are

caused by transitory events, therefore the error condition is latched (marked with an ‘L’).

Reading this status register causes all latched bits to be set inactive unless an error event is

currently pending.

Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set

Low) if the source of the interrupt has not been masked in the corresponding Mask register.

Bit

Name

Active State

Function

RxDataPathQOF

High

Data path gain, phase and offset (GPO) adjustment unit: Q

channel overflow error status bit.

RxDataPathIOF

High

Data path gain, phase and offset (GPO) adjustment unit:

I channel overflow error status bit.

AdcQOF

High

ADC Q channel overflow error due to excessive input

amplitude.

AdcIOF

High

ADC I channel overflow error due to excessive input

amplitude.

Rx63tapOF

High

63-tap I and Q filter data accumulator overflow error status

bit.

Rx49tapOF

High

49-tap I and Q filter data accumulator overflow error status

bit.

EvenSamplePhase

High

When this status bit is active, the associated interrupt may

be used to re-synchronise the Rx data if for any reason

data synchronisation is lost. If the corresponding mask bit

is set inactive, an interrupt will be generated on the next

Q-phase data in the Rx output register. The next falling

edge of SClk with RxFS High indicates the LSB of the Q

channel data. The mask bit should be disabled after this to

prevent continuous Q-phase interrupts.

RxIrqActive

High

This bit is set High if there is an active interrupt caused by

one of the status bits in this register.

• Address and Data format for RxErrorStatus access

D1 D0

D7 D6 D5 D4 D3 D2

Data field [7:0]

Address field [6:0]

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