FX980 datasheet(61/86 Pages) CMLMICRO

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TETRA Baseband Processor

FX980

D/980/3

TxDataAccess

Title:

Tx Data path Access point.

Address:

$0x50 to $0x53 (mapped over 4 locations)

Function:

Description:

This register block allows direct access to the Tx Data path values just after the gain, phase and

offset adjustment block. Both read and write operations are permitted. A read operation reads

the signal values on the I and Q channels. A write operation will write data to the data path just

before the 15-tap filter. To prevent normal Tx data overwriting this value the TxDPAccessSel bit

in the LoopBackCtrl register should be set active. The MSB read data register is buffered to

enable access to a discrete sample value (if this register was not buffered, data from different

sample periods could be in the MSB and LSB registers). Therefore the LSB register must be

read first for correct operation.

Bit

Name

Active State

Function

Address $0x50

7:0

TxDPIDataLSB

Data RW

Least significant 8 bits of the TxDPIData register. This

Address $0x51

7:4

Reserved. Set these bits Low. Undefined on read.

3:0

TxDPIDataMSB

Data RW

Most significant 2 bits of the TxDPIData register.

Address $0x52

7:0

TxDPQDataLSB

Data RW

Least significant 8 bits of the TxDPQData register. This

Address $0x53

7:4

Reserved. Set these bits Low. Undefined on read.

3:0

TxDPQDataMSB

Data RW

Most significant 2 bits of the TxDPQData register.

FX980 Datasheet(PDF) 61 Page - CML Microcircuits

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