FX980 datasheet(57/86 Pages) CMLMICRO

57 / 86 page

TETRA Baseband Processor

FX980

D/980/3

TxIQOffset

Title:

Transmit I and Q channel Offset correction register

Address:

$0x44, $0x45, $0x4A, and $0x4B (4 locations)

Function:

Description:

This register controls the Tx Data path signal offset. This offset is a 2s-complement value

offset), which is applied to the Tx signal after the Gain Multiplier (Gval), but before the DAC. The

offset applied is at the discretion of the user. Inappropriate values may cause arithmetic

overflow in the subsequent operator sections. The result is given by the formula:

D +

out

offset













Where:

Din

Dout

offset

is the signal input,

is the signal output,

is the 2s-complement value in the

Bit

Name

Active State

Function

Address $0x44

7:0

TxIOffsetLSB

Data RW

Least significant 8 bits of the TxIOffset register (N

offset).

Address $0x45

7:4

Reserved. Set these bits Low. Undefined on read.

3:0

TxIOffsetMSB

Data RW

Most significant 4 bits of the TxIOffset register (N

offset).

Address $0x4A

7:0

TxQOffsetLSB

Data RW

Least significant 8 bits of the TxQOffset register (N

offset).

Address $0x4B

7:4

Reserved. Set these bits Low. Undefined on read.

3:0

TxQOffsetMSB

Data RW

Most significant 4 bits of the TxQOffset register (N

offset).

FX980 Datasheet(PDF) 57 Page - CML Microcircuits

FX980 Datasheet(HTML) 57 Page - CML Microcircuits

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL