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FX980 Datasheet(PDF) 25 Page - CML Microcircuits |
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FX980 Datasheet(HTML) 25 Page - CML Microcircuits |
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25 / 86 page  TETRA Baseband Processor FX980 © 1997 Consumer Microcircuits Limited 25 D/980/3 Read operation Bit Name Active State Function Address $0x04 7:2 Reserved. Bit values are not defined. 1:0 UpperFIFORdData Data R Reads address access bits 9 and 8 of the FIFO data output register, these are placed in bits 1 and 0. Address $0x05 7:0 LowerFIFORdData Data R Reads address access bits 7 to 0 of the FIFO data output register. Reading this location also performs a FIFO read operation, thereby moving the next (if any) FIFO data location into the FIFO data output register. Address $0x06 and $0x07 7:0 R Reserved. Bit values are not defined. For these read operations to be valid, the Tx Data path must be active (TxEn bit of TxSetup register set active) and the SymbModuBypass bit of the ConfigCtrl1 register must also be set active. |
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