FX980 datasheet(59/86 Pages) CMLMICRO

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TETRA Baseband Processor

FX980

D/980/3

TxPhase

Title:

Transmit I and Q channel Phase correction register

Address:

$0x40, $0x41, $0x46, $0x47 (4 locations)

Function:

Description:

This register controls the Tx Data path I and Q channel phase compensation. The phase may

be adjusted by

±7.1° with respect to the input data signal phase. As each channel has separate

phase adjustments the maximum differential phase compensation that can be achieved is

±14.2°. The phase adjustment value written to this register is a 2s-complement value (N

phase).

The amount of phase adjustment applied is given by the formula:

tan

- 1

phase













Where:

phase

is the phase adjustment,

is the value in the register and has

a range of -256 to +255.

Note: Although each channel is separately adjustable with its own compensation value, the

effect of phase adjustment is only detectable by measuring the phase angle between I and Q

channels. It should be noted that the N

phase

value has the effect of lagging the I channel for

positive values of N

phase (conversely, leading the phase for negative values) and leading the Q

channel for positive values of N

phase

(conversely, lagging the phase for negative values). For

example, putting the value 10 (decimal) into both TxIPhase and TxQPhase would produce a

differential phase on I and Q of:

o - 2(tan-1(4.88x10-3)) = 89.44o

Bit

Name

Active State

Function

Address $0x40

7:0

TxIPhaseLSB

Data RW

Least significant 8 bits of the TxIPhase register (N

phase).

Address $0x41

7:1

Reserved. Set these bits Low. Undefined on read.

TxIPhaseMSB

Data RW

Most significant bit of the TxIPhase register (sign bit).

Address $0x46

7:0

TxQPhaseLSB

Data RW

Least significant 8 bits of the TxQPhase register (N

phase).

Address $0x47

7:1

Reserved. Set these bits Low. Undefined on read.

TxQPhaseMSB

Data RW

Most significant bit of the TxQPhase register (sign bit).

FX980 Datasheet(PDF) 59 Page - CML Microcircuits

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