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FX980 Datasheet(PDF) 69 Page - CML Microcircuits |
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FX980 Datasheet(HTML) 69 Page - CML Microcircuits |
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69 / 86 page  TETRA Baseband Processor FX980 © 1997 Consumer Microcircuits Limited 69 D/980/3 BISTPRSG Title: Built In Self Test Pseudo Random Sequence Generator Address: $0x60 to $0x61 (2 locations) Function: RW Description: This register block allows control of BIST operations. This 16-bit number controls the length of the BIST data sequence. It is the initial value (or seed) written to the pseudo-random sequence generation logic. The length of the BIST data sequence is a function of the feedback logic equation and this initial value. The feedback function is fixed so run lengths are therefore controlled by this value. Which values to apply to give specific run lengths can be determined from a look-up table. This table may be provided on request. Bit Name Active State Function Address $0x60 7:0 BISTPRSGLSB Data RW Least significant 8 bits of the BISTPRSG register. This register must be read before its associated MSB register. Address $0x61 7:0 BISTPRSGMSB Data RW Most significant 8 bits of the BISTPRSG register. This register must be read after its associated LSB register. • Address and Data format for BISTPRSG access D1 D0 D7 D6 D5 D4 D3 D2 D15 D14 D13 D12 D11 D10 D9 D8 0 Data field [15:0] 1 Address field [6:0] 1 0 0 0 0 1 1 0 0 0 0 1 |
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