FX980 datasheet(45/86 Pages) CMLMICRO

45 / 86 page

TETRA Baseband Processor

FX980

D/980/3

TxFIFOStatus

Title:

Transmit data FIFO Status register

Address:

$0x22

Function:

Description:

This register is the Tx Data FIFO status register. The TxIrqActive bit is set active when one of

the other bits in this register is the source of an interrupt event. Some of these status conditions

are caused by transitory events, therefore their state is latched (marked with an ‘L’). The bits

marked with a parenthesised ‘L’ are only latched in their interrupt generation state if their

associated mask bit is inactive. Reading this status register causes all latched bits to be set

inactive, unless an error event is currently pending.

Setting any bit of this register High will cause an interrupt to be generated (N_IRQ will be set

Low) if the source of the interrupt has not been masked in the corresponding Mask register.

Bit

Name

Active State

Function

TxPathEn

High/

Low

R(L)

When active (High) this bit shows that the Tx Data

path is currently active. This enables the user to

confirm that ramp down has completed.

For interrupt generation purposes, a logic Low on

this bit will be considered as active.

FIFOUnderRead

High

Error status bit. When active indicates a read from

the FIFO occurred while the FIFO was empty.

FIFOOverWrite

High

Error status bit. When active indicates a write to the

FIFO occurred while the FIFO was full.

FIFOFull

High/

Low

R(L)

Most significant FIFO length status bit. When active

(High) this bit also indicates the FIFO is full.

For interrupt generation purposes, a logic Low on

this bit will be considered as active.

3:2

FIFOLength

(Low) R(L)

These two bits contain the pointer to the next free

FIFO address and indicate the following status:

00 - indicates FIFO is empty

01 - one location used

10 - two locations used

11 - three locations used

For interrupt generation purposes, a logic Low on

either of these bits will be considered as active.

FIFOEmpty

High

R(L)

When active indicates the FIFO is empty.

FifoIrqActive

High

This bit is set High if there is an active interrupt

caused by one of the status bits in this register.

FX980 Datasheet(PDF) 45 Page - CML Microcircuits

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