FX980 datasheet(17/86 Pages) CMLMICRO

17 / 86 page

TETRA Baseband Processor

FX980

D/980/3

Rx Data Path Access Points

$0x38-$0x39

RxDataAccess

Receive path data access point (I)

$0x3A-$0x3B

RxDataAccess

Receive path data access point (Q)

$0x3C-$0x3F

Not Used

Tx Data Path Registers

$0x40-$0x41

TxPhase

Transmit I channel phase correction registers

$0x42-$0x43

TxIQGainMult

Transmit I channel gain attenuation registers

$0x44-$0x45

TxIQOffset

Transmit I channel offset correction registers

$0x46-$0x47

TxPhase

Transmit Q channel phase correction registers

$0x48-$0x49

TxIQGainMult

Transmit Q channel gain attenuation registers

$0x4A-$0x4B

TxIQOffset

Transmit Q channel offset correction registers

$0x4C-$0x4D

TxRampUpInc

Transmit ramp-up increment registers

$0x4E-$0x4F

TxRampDnDec

Transmit ramp-down decrement registers

Tx Data Path Access Points

$0x50-$0x51

TxDataAccess

Transmit path data access point (I)

$0x52-$0x53

TxDataAccess

Transmit path data access point (Q)

$0x54-$0x5F

Not Used

Self Test Registers

$0x60-$0x61

BISTPRSG

Built-in self test pseudo-random sequence generator

$0x62

BISTControl

Built-in self test control register

$0x63

Not Used

$0x64-$0x6D

BISTCRCRegisters

Built-in self test cyclic redundancy code checkers

$0x6E-$0x6F

Not Used

SRAM Memory Access Points

$0x70-$0x73

SramData

Auxiliary DAC1 memory I/O access addresses

$0x74-$0x7F

Not Used

Note: Addresses $0x80 to $0xFF cannot be used as the MSB controls the direction of data flow:

“1” = High = Read and “0” = Low = Write.

FX980 Datasheet(PDF) 17 Page - CML Microcircuits

FX980 Datasheet(HTML) 17 Page - CML Microcircuits

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