FX980 datasheet(68/86 Pages) CMLMICRO

68 / 86 page

TETRA Baseband Processor

FX980

D/980/3

BISTControl

Title:

Built In Self Test Control register

Address:

$0x62

Function:

Description:

This register block allows control of BIST operations.

Bit

Name

Active State

Function

TestCompleteAck

High/

Low

This bit is set by the user and cleared by the BIST

controller when a BIST cycle has been completed.

n_RampDelayEn

Low RW

Allow Ramp control signal delay. This delay is required

for normal operations, by matching the FIR filter delays.

For BIST operations it can be disabled thus reducing BIST

test time.

BISTDataRateHi

High RW

Selects BIST data rate = 2.34 MHz

Default rate (Low)

= 1.44 kHz

BISTEn

High RW

Enables BIST operations.

ContinuousBIST

High RW

Selects continuous BIST mode.

Default (Low) selects single cycle mode.

EnRxDigitalFeedBack

High RW

Selects Rx digital loop feedback for 49-tap Tx FIR input

data. Default (Low) selects normal Tx data.

En49tlQData

High RW

Selects BIST data for 49-tap Tx FIR filter input.

Default (Low) selects normal data.

EnSymTestData

High RW

Selects BIST data for 79-tap FIR filter input.

Default (Low) selects normal data.

• Address and Data format for BistControl access

D1 D0

D7 D6 D5 D4 D3 D2

Data field [7:0]

Address field [6:0]

FX980 Datasheet(PDF) 68 Page - CML Microcircuits

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