FX980 datasheet(48/86 Pages) CMLMICRO

48 / 86 page

TETRA Baseband Processor

FX980

D/980/3

CoeffRamData

Title:

I/O access addresses for the five coefficient memories.

Address:

$0x24 to $0x2D (mapped over 10 locations)

Function:

Description:

Each coefficient RAM has both MSB and LSB address ports assigned for read/write access.

There are three transmit (Tx) FIR filters with read/write coefficients and two receive (Rx) filters,

with coefficient sizes of 12 and 16 bits respectively. Access to the coefficient memory is valid

when the CoeffRamIoEn bit is active.

Asserting the CoeffRamIoEn will reset the Coefficient Address Pointer to the first location (A1).

The MSB port should be accessed first, as accessing the LSB port will move the Coefficient

Address Pointer

the

coefficient

location

(A[n+1])

(refer

description

CoeffRamIoRdInc bit for details).

Subsequent accesses to the LSB port of the coefficient

address will increment the Coefficient Address Pointer.

As all filters are symmetrical and “odd”, only

+ 1

locations can be programmed, where N is

the filter tap length. Performing an I/O access after the last Coefficient Address Pointer is not

valid, and may corrupt existing coefficients. Only one FIR filter coefficient RAM may be

accessed at a time. If further memories are to be accessed then the CoeffRamIoEn must first

be deactivated, and then activated again, allowing the next FIR filter coefficient RAM to be

incrementally accessed.

Bit

Name

Active State

Function

Address $0x24

7:0

Tx15tapCoeffLSB

Data RW

Transmit 15-tap filter LSB coefficient data port.

Post-increment the coefficient address pointer.

Address $0x25

7:4

Reserved. Set these bits High. Undefined on read.

3:0

Tx15tapCoeffMSB

Data RW

Transmit 15-tap filter MSB coefficient data port.

Address $0x26

7:0

Tx49tapCoeffLSB

Data RW

Transmit 49-tap filter LSB coefficient data port.

Post-increment the coefficient address pointer.

Address $0x27

7:4

Reserved. Set these bits High. Undefined on read.

3:0

Tx49tapCoeffMSB

Data RW

Transmit 49-tap filter MSB coefficient data port.

Address $0x28

7:0

Tx79tapCoeffLSB

Data RW

Transmit 79-tap filter LSB coefficient data port.

Post-increment the coefficient address pointer.

Address $0x29

7:4

Reserved. Set these bits High. Undefined on read.

3:0

Tx79tapCoeffMSB

Data RW

Transmit 79-tap filter MSB coefficient data port.

Address $0x2A

7:0

Rx49tapCoeffLSB

Data RW

Receive 49-tap filter LSB coefficient data port.

Post-increment the coefficient address pointer.

FX980 Datasheet(PDF) 48 Page - CML Microcircuits

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