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AM3892 Datasheet(PDF) 146 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 146 Page - Texas Instruments |
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146 / 299 page  AM3894 AM3892 SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 www.ti.com 7.4.2 Cortex™-A8 Interrupts The Cortex™-A8 Interrupt Controller (AINTC) takes ARM device interrupts and maps them to either the interrupt request (IRQ) or fast interrupt request (FIQ) of the ARM with an individual priority level. The AINTC interrupts must be active low-level interrupts. The AINTC is responsible for prioritizing all service requests from the system peripherals directed to the Cortex™-A8 SS and generating either nIRQ or nFIQ to the host. The type of the interrupt (nIRQ or nFIQ) and the priority of the interrupt inputs are programmable. It has the capability to handle up to 128 requests which can be steered/prioritized as nFIQ or nIRQ interrupt requests. The general features of the AINTC are: • Up to 128 level-sensitive interrupts inputs • Individual priority for each interrupt input • Each interrupt can be steered to nFIQ or nIRQ • Independent priority sorting for nFIQ and nIRQ • Secure mask flag. Table 7-18. Cortex™-A8 Interrupt Controller Connections INTERRUPT ACRONYM SOURCE NUMBER 0 EMUINT Internal 1 COMMTX Internal 2 COMMRX Internal 3 BENCH Internal 4 ELM_IRQ ELM 5-6 - 7 NMI External Pin 8 - 9 L3DEBUG L3 10 L3APPINT L3 11 - 12 EDMACOMPINT TPCC 13 EDMAMPERR TPCC 14 EDMAERRINT TPCC 15 - 16 SATAINT SATA 17 USBSSINT USBSS 18 USBINT0 USBSS 19 USBINT1 USBSS 20-33 - 34 USBWAKEUP USBSS 35 PCIeWAKEUP PCIe 36 DSSINT HDVPSS 37 GFXINT SGX530 (AM8394 only) 38 HDMIINT HDMI 39 - 40 MACRXTHR0 EMAC0 41 MACRXINT0 EMAC0 42 MACTXINT0 EMAC0 146 Power, Reset, Clocking, and Interrupts Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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