AM3892 datasheet(150/299 Pages) TI

150 / 299 page

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.1.3

Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routings. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

For the DDR2/3, PCIe, SATA, USB, and HDMI interfaces, IBIS models are not used for timing

specification. TI provides, in this document, a PCB routing rule solution for each interface that describes

the routing rules used to ensure the interface timings are met. Video DAC guidelines (Section 8.10.3) are

also included to discuss important layout considerations.

8.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

150

Peripheral Information and Timings

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AM3892 Datasheet(PDF) 150 Page - Texas Instruments