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AM3892 Datasheet(PDF) 152 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 152 Page - Texas Instruments |
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152 / 299 page  DDR[x]_D[0] DDR[x]_D[7] DDR[x]_DQM[0] DDR[x]_DQS[0] DDR[x]_DQS[0] DDR[x]_D[8] DDR[x]_D[15] DDR[x]_DQM[1] DDR[x]_DQS[1] DDR[x]_DQS[1] DQ0 DQ7 LDM LDQS LDQS DQ8 DQ15 UDM UDQS UDQS BA0 BA2 A0 A14 CS CAS RAS WE CKE CK CK VREF DQ0 DQ7 LDM LDQS LDQS DQ8 DQ15 UDM UDQS UDQS BA0 BA2 A0 A14 CS CAS RAS WE CKE CK CK VREF DDR_D16 DDR[x]_D[23 DDR[x]_DQM[2] DDR[x]_DQS[2] DDR[x]_DQS[2] DDR[x]_D[24] DDR[x]_D[31] DDR[x]_DQM[3] DDR[x]_DQS[3] DDR[x]_DQS[3] DDR[x]_BA[0] DDR[x]_BA[2] DDR[x]_A[0] DDR[x]_A[14] DDR[x]_CS[0] DDR[x]_CAS DDR[x]_RAS DDR[x]_WE DDR[x]_CKE DDR[x]_CLK[x] DDR[x]_CLK[x] ODT VREFSSTL_DDR[x] 1 K 1% Vio 1.8 (A) DDR2 DDR2 VREF 0.1 µF VREF VREF 0.1 µF 1 K 1% 0.1 µF (B) 0.1 µF (B) DDR_ODT1 NC ODT 50 2 (± %) DDR[x]_VTP 0.1 µF (B) T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 T0 Termination is required. See terminator comments. DDR[x]_ODT[0] DDR[x]_CS[1] NC DDR[x]_RST NC AM3894 AM3892 SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 www.ti.com A. Vio1.8 is the power supply for the DDR2 memories and the AM389x DDR2 interface. B. One of these capacitors can be eliminated if the divider and its capacitors are placed near a VREF pin. Figure 8-5. 32-Bit DDR2 High-Level Schematic 152 Peripheral Information and Timings Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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