AM3892 datasheet(151/299 Pages) TI

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DDR_CLK

AM3894

AM3892

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SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

8.3

DDR2/3 Memory Controller

The device has a dedicated interface to DDR3 and DDR2 SDRAM. It supports JEDEC standard-compliant

DDR2 and DDR3 SDRAM devices with the following features:

•

16-bit or 32-bit data path to external SDRAM memory

•

Memory device capacity: 64Mb, 128Mb, 256Mb, 512Mb, 1Gb, and 2Gb devices

•

Support for two independent chip selects, with their corresponding register sets, and independent page

tracking

•

Two interfaces with associated DDR2/3 PHYs

•

Dynamic memory manager allows for interleaving of data between the two DDR interfaces.

For details on the DDR2/3 Memory Controller, see the DDR2/3 Memory Controller chapter in the AM38x

Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

8.3.1

DDR2 Routing Guidelines

CAUTION

The DDR2 Routing Guidelines are preliminary and are being verified by design

simulations.

8.3.1.1

Board Designs

TI only supports board designs that follow the guidelines outlined in this document. The switching

characteristics and the timing diagram for the DDR2 memory controller are shown in Table 8-1 and

Figure 8-4.

Table 8-1. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory

Controller

-1G

NO.

PARAMETER

UNIT

MIN

MAX

tc(DDR_CLK)

Cycle time, DDR_CLK

2.5

Figure 8-4. DDR2 Memory Controller Clock Timing

8.3.1.2

DDR2 Interface

This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing

specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,

and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need

for a complex timing closure process. For more information regarding the guidelines for using this DDR2

specification, see Understanding TI’s PCB Routing Rule-Based DDR2 Timing Specification Application

Report (SPRAAV0).

8.3.1.2.1 DDR2 Interface Schematic

Figure 8-5 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-6 the x16

DDR2 system schematic is identical except that the high-word DDR2 device is deleted.

Peripheral Information and Timings

151

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