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AM3892 Datasheet(PDF) 217 Page - Texas Instruments

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Part # AM3892
Description  AM389x Sitara ARM Microprocessors (MPUs)
PDF  299 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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AM3892 Datasheet(HTML) 217 Page - Texas Instruments

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AM3894
AM3892
www.ti.com
SPRS681A – OCTOBER 2010 – REVISED MARCH 2011
Table 8-58. Switching Characteristics Over Recommended Operating Conditions for GPMC/NOR Flash
Interface - Asynchronous Mode (continued)
(see Figure 8-57, Figure 8-58, Figure 8-59, Figure 8-60, Figure 8-61, Figure 8-62)
NO.
PARAMETER
MIN
MAX
UNIT
15
td(nCSV-DIR)
Delay time, GPMC_CS[x] valid to GPMC_DIR high
L - 0.2(7)
L + 2.0(7)
ns
16
td(nCSV-DIR)
Delay time, GPMC_CS[x] valid to GPMC_DIR low
M - 0.2(8)
M + 2.0(8)
ns
17
tw(AIV)
Address invalid duration between 2 successive R/W accesses
G(9)
ns
Delay time, GPMC_CS[x] valid to GPMC_OE_RE invalid (burst
19
td(nCSV-nOEIV)
I - 0.2(10)
I + 2.0(10)
ns
read)
21
tw(AV)
Pulse duration, address valid: second, third and fourth accesses
D(11)
ns
26
td(nCSV-nWEV)
Delay time, GPMC_CS[x] valid to GPMC_WE valid
E - 0.2(12)
E + 2.0(12)
ns
28
td(nCSV-nWEIV)
Delay time, GPMC_CS[x] valid to GPMC_WE invalid
F - 0.2(13)
F + 2.0(13)
ns
29
td(nWEV-DV)
Delay time, GPMC_WE valid to data bus valid
2.0
ns
30
td(DV-nCSV)
Delay time, data bus valid to GPMC_CS[x] valid
J - 0.2(5)
J + 2.0(5)
ns
Delay time, GPMC_OE_RE valid to GPMC_A[16:1]_D[15:0]
38
td(nOEV-AIV)
2.0
ns
address phase end
(8)
= M - nCS Max Delay + nOE Min Delay
M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK.
Parameter M expression is given as one example of GPMC programming. The IO DIR signal goes from IN to OUT after both
RdCycleTime and BusTurnAround completion. Behavior of the IO direction signal depends on the kind of successive read/write
accesses performed to the memory and multiplexed or non-multiplexed memory addressing scheme, whether the bus keeping feature is
enabled or not. The IO DIR behavior is automatically handled by the GPMC controller.
(9)
G = Cycle2CycleDelay * GPMC_FCLK
(10) = I - nCS Max Delay + nOE Min Delay
I = ((OEOffTime + (n - 1) * PageBurstAccessTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay - CSExtraDelay)) *
GPMC_FCLK
(11) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(12) = E - nCS Max Delay + nWE Min Delay
E = ((WEOnTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
(13) = F - nCS Max Delay + nWE Min Delay
F = ((WEOffTime - CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay - CSExtraDelay)) * GPMC_FCLK
Copyright © 2010–2011, Texas Instruments Incorporated
Peripheral Information and Timings
217
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