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AM3892 Datasheet(PDF) 249 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 249 Page - Texas Instruments |
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249 / 299 page  AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 8.12.2 McASP0, McASP1, and McASP2 Peripheral Register Descriptions Table 8-77. McASP0/1/2 Registers MCASP0 ADDRESS MCASP1 ADDRESS MCASP2 ADDRESS ACRONYM REGISTER NAME 0x4803 8000 0x4803 C000 0x4805 0000 PID Peripheral ID 0x4803 8004 0x4803 C004 0x4805 0004 PWRIDLE Power Idle SYSCONFIG SYSCONFIG 0x4803 8010 0x4803 C010 0x4805 0010 PFUNC Pin Function 0x4803 8014 0x4803 C014 0x4805 0014 PDIR Pin Direction 0x4803 8018 0x4803 C018 0x4805 0018 PDOUT Pin Data Out PDIN Pin Data Input (Read) Read returns pin data input PDSET Pin Data Set (Write) 0x4803 801C 0x4803 C01C 0x4803 C01C Writes effect pin data set (alternate write address PDOUT) 0x4803 8020 0x4803 C020 0x4805 0020 PDCLR Pin Data Clear 0x4803 8044 0x4803 C044 0x4805 0044 GBLCTL Global Control 0x4803 8048 0x4803 C048 0x4805 0048 AMUTE Mute Control 0x4803 804C 0x4803 C04C 0x4805 004C LBCTL Loop-Back Test Control 0x4803 8050 0x4803 C050 0x4805 0050 TXDITCTL Transmit DIT Mode Control 0x4803 8060 0x4803 C060 0x4805 0060 GBLCTLR Alias of GBLCTL containing only receiver reset bits; allows transmit to be reset independently from receive 0x4803 8064 0x4803 C064 0x4805 0064 RXMASK Receiver Bit Mask 0x4803 8068 0x4803 C068 0x4805 0068 RXFMT Receive Bitstream Format 0x4803 806C 0x4803 C06C 0x4805 006C RXFMCTL Receive Frame Sync Control 0x4803 8070 0x4803 C070 0x4805 0070 ACLKRCTL Receive Clock Control 0x4803 8074 0x4803 C074 0x4805 0074 AHCLKRCTL High Frequency Receive Clock Control 0x4803 8078 0x4803 C078 0x4805 0078 RXTDM Receive TDM Slot 0-31 0x4803 807C 0x4803 C07C 0x4805 007C EVTCTLR Receiver Interrupt Control 0x4803 8080 0x4803 C080 0x4805 0080 RXSTAT Status Receiver 0x4803 8084 0x4803 C084 0x4805 0084 RXTDMSLOT Current Receive TDM Slot 0x4803 8088 0x4803 C088 0x4805 0088 RXCLKCHK Receiver Clock Check Control 0x4803 808C 0x4803 C08C 0x4805 008C REVTCTL Receiver DMA Event Control 0x4803 80A0 0x4803 C0A0 0x4805 00A0 GBLCTLX Alias of GBLCTL containing only transmit reset bits; allows transmit to be reset independently from receive 0x4803 80A4 0x4803 C0A4 0x4805 00A4 TXMASK Transmit Format Unit Bit Mask 0x4803 80A8 0x4803 C0A8 0x4805 00A8 TXFMT Transmit Bitstream Format 0x4803 80AC 0x4803 C0AC 0x4805 00AC TXFMCTL Transmit Frame Sync Control 0x4803 80B0 0x4803 C0B0 0x4805 00B0 ACLKXCTL Transmit Clock Control 0x4803 80B4 0x4803 C0B4 0x4805 00B4 AHCLKXCTL High Frequency Transmit Clock Control 0x4803 80B8 0x4803 C0B8 0x4805 00B8 TXTDM Transmit TDM Slot 0-31 0x4803 80BC 0x4803 C0BC 0x4805 00BC EVTCTLX Transmitter Interrupt Control 0x4803 80C0 0x4803 C0C0 0x4805 00C0 TXSTAT Status Transmitter Copyright © 2010–2011, Texas Instruments Incorporated Peripheral Information and Timings 249 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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